1. Field of the Invention
The invention relates to a computing method and a computing apparatus which executes a double-precision multiplication by using a single-precision multiplying device.
2. Description of the Prior Art
Conventionally, a double-precision multiplication system is known in which products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device and a digit place alignment addition operation is performed on each of the products, thereby obtaining a double-precision multiplication result. This system is disclosed in, for example, Japanese patent publication (Kokai) No. HEI8-30439. In the prior art example disclosed in Japanese patent publication (Kokai) No. HEI8-30439, means for holding the most significant bit of low-word of a double-precision multiplier is disposed, and the most significant bit of the low-order word of the double-precision multiplier is used in the encoding of the high-order word of the double-precision multiplier, so that the low-order word of the double-precision multiplier is treated as a signed binary. In order to perform a multiplication of the low-order word of the double-precision multiplicand, the system is provided with multiplying means having a function of enabling a multiplication even when the multiplicand is an unsigned binary. Therefore, the prior art technique can realize a double-precision multiplication without impairing the precision.
In the prior art example disclosed in Japanese patent publication (Kokai) No. HEI8-30439, however, a sign indicative of a positive number is assumed at the bit which is higher by one bit than the most significant bit of a multiplicand, when the multiplying means treats the multiplicand as an unsigned binary. Therefore, the digit place of the sign of the multiplication result is different from that of a result of a multiplication in which the multiplicand is a signed binary. Consequently, the shift number for digit place alignment is different in additions of products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier, and hence the prior art example has a problem in that the circuit scale for digit place aligning means becomes large.